Took it with TA Sam Lee
definitely made it easier for me!
GOAT

Boring class.

I took this class in Winter 2022, and it was really different from what you'd expect from a class. The class is entirely run by the TA. I didn't even see the professor once. Also, I don't know why we have to take this class. It's literally useless. You'll find that the projects aren't too hard, but you can get into trouble by running into 1000 problems with their outdated software. I had Samuel Lee for this class, who was extremely helpful and lenient. I talked to my friends from the other sections, and they mentioned that they were simply given the spec and instructed to read it themselves and do the projects. Sam studies all the projects and picks out parts that he thinks will be difficult for us, and he legit made an entire slide deck going over difficult concepts and how we should do the projects. He's also super reasonable, so if you go to his office hours and talk to him, he's likely to help you out. I give the class a 7/10 cause the class sucked, but the overall experience wasn't bad.

You should expect 4 labs. The first two labs are fairly easy. The third lab might wreck you, but if you go to office hours you can survive. The fourth lab is a project of your choice (HINT: CHOOSE AN EASY PROJECT GUYS).

Boring and useless class. But like what others said, a good TA (and parter) will save you tons of effort. The projects are fairly easy and the spec is mostly clear (unlike the shitty 152B). You can find past solutions online. Writing reports is tedious, time-consuming but not difficult. For the final project which you can make on your own, I suggest working on something simple, because a complicated one will not bring you much grade boost and will likely cause trouble.

Fuck this class. It's fucking useless.

shuwen qiu my queen

First off, this class is not with the professor listed - you will spend the entirety of it with an assigned TA. Also, you will spend the entirety of it with a partner/group that you will choose at the first lab section, so if you want to minimize the risk of being paired with a useless partner, I recommend you sign up for this class with a friend. In this class, you will be learning Verilog and implementing some designs on an FPGA (circuit board) in Verilog. It's a pretty cool class I thought, as you get to get hands-on experience and see what computers are capable of even at a low level, but it's knowledge that won't really be too useful if you're going the software engineering route. In terms of workload, my partner and I handled pretty much all of our workload in class in terms of getting the code done, however there are open lab hours which we used maybe once or twice to be sure we would finish an assignment on time (you need to be physically present with the FPGA for testing, so can't do any testing on your own machine). Apart from that, there are lab reports that you need to do, but these usually would not take more than 2-3 hours per report, and there were only 4 or 5 of them throughout the entirety of the quarter.

Somehow they still don't get rid of this class yet. I couldn't contribute much to my team because the instructions were always unclear and I didn't even know where to start every lab. I was lucky enough to have a smart partner who literally carried the whole team but I ended up finishing this class learning nothing. We spent hours outside of class to develop the final project and it was exhasting. Hope I don't have to see Verilog again even though I'm a CSE major.

My TA for this class was Weitong Zhang. He did a good job lecturing and going over the project specs.
The class consisted of four projects. Before each project, the TA would give a lecture going over the spec, and the rest of the sections were just office hours. The projects primarily consisted of manipulating clocks and building FSMs using Verilog. It wasn't too difficult, and mainly built off of concepts from CS M51A/ECE M16. The projects were due every 2-3 weeks, which is more than enough time to complete them.

Ok so this class was with a TA, and I had Weitong Zhang, who was very friendly and helpful. The class is honestly pretty easy: there is 1-2 lectures about the next project, then the rest of the sections are OH until the project is due. It was relaxed.

There are 4 labs. The labs got a little hard at the end, but mostly if you pay attention to the pre-lab and use good practice for clocking, then you're A-OK.
The "code" is all done in Verilog, which is actually a description language (like HTML is to webpages): it describes digital systems, but doesn't "code" more than define behavior on certain signals. I say this bc it's a little hard to grasp at first, but easy once you get the hang of it. I did all the projects in <15 hours. If you design your module correctly, write good test cases, and make a lab report with all the right components, you get an A.